An IC chip of semiconductor silicon in present-day art can contain as many as several hundred thousand or even a million transistors. Electrical access to these transistors from one or more other silicon chips is limited by the number of input/output (I/O) ports, typically in the form of metallic pads, that can be fitted on the chip and be reliably electrically connected via metallic interconnection wiring to other chips. This limit on the number of I/O ports per chip undesirably limits the circuit design versatility of an IC chip and undesirably proliferates the number of chips required in IC technology for implementing a given electrical circuit.
One of the difficulties associated with any scheme for establishing chip-to-chip interconnections is that these interconnections must be accomplished with finished chips--i.e., chips having their integrated circuitry completed--so that by the time they are ready for chip-to-chip interconnections, the chips cannot withstand temperatures much above 300.degree. C. or so without damaging their integrated circuitry.
In a paper entitled "Wafer-Chip Assembly for Large-Scale Integration" by P. Kraynak et al published in IEEE Transactions on Electron Devices, vol. ED-15 (1968), pp. 660-663, a chip-to-chip interconnection scheme is described in which the circuit face of each chip has a plurality of smooth metallic I/O pads, typically made of gold or aluminum. Each chip is oriented circuit-face-downward so that each of these pads (hereinafter "chip pads") is located in registry with a corresponding one of a plurality of smooth metallic pads located on a top surface of a flat silicon wafer serving as a chip-carrier (hereinafter "carrier"). The top surface of the carrier is coated with an insulating layer upon which a pattern of interconnection wiring, typically of aluminum, is deposited in accordance with a desired chip-to-chip electrical interconnection pattern. The pads on the top surface of the carrier (hereinafter "carrier pads") typically are simply formed by those portions of this chip-to-chip electrical interconnection wiring on the carrier which directly underlie (in registry with) the chip pads. Relatively low resistance contact-bonding between each carrier pad and its corresponding (in registry) chip pad is achieved by forming a metallic bump or glob of suitable metal--such as gold or solder--on each carrier pad or on each chip pad, or on both, followed by bonding each carrier pad to its corresponding chip pad by means of an ultrasonic, thermo-compression, or solder-reflow bonding technique. The area of the top surface of the carrier is advantageously considerably larger than the area of a single chip. Thus more than one such chip can similarly be bonded onto a single carrier. The carrier, together with its interconnection wiring, thus serves as a chip-to-chip electrical interconnection means for the chips, as well as a thermal sink and a mechanical support member for each chip.
A problem that arises in the prior art is that the surface of the chip in general is bowed (curved) and hence not sufficiently flat to enable all metallic globs to come in contact with and be bonded to the corresponding carrier pads unless such high compressive forces be applied as to risk breaking the chip.